This invention relates to a circuit for testing current voltage conversion amplifiers designed for use with photo diodes. It is a primary object of the present invention to provide a circuit for testing a current-voltage conversion amplifier having a photodiode without exposing light to the photodiode. Conventionally, the current voltage conversion amplifiers can also be called as transimpedance amplifiers.
FIG. 1 shows a conventional transimpedance amplifier 100 having a photodiode 110 connected to the input terminal 121 of the amplifier 120. When the photodiode 110 is exposed to light, the photodiode 110 sinks (sources) a current I from (to) the transimpedance amplifier 120. The current is then converted into a voltage VOUT at the output terminal by the transimpedance amplifier 120. The output voltage of the transimpedance amplifier 120 is proportional to the light intensity received by the photodiode 110. Generally the photodiode 110 and transimpedance amplifier 120 combination can be incorporated into a single integrated circuit, onto the same semiconductor substrate material. This is the current trend of systems-on-a-chip, or systems integration. In these cases, the testing of the transimpedance amplifier 120 becomes an issue.
Conventionally, the testing of the photodiode-and-transimpedance-amplifier combination can only be performed by actually exposing the photodiode 11xe2x80x94to light and then obtaining an output voltage from the transimpedance amplifier 120 output, because no external (test-input) access pin can be placed at the connection between the photodiode 110 and the transimpedance amplifier 120, due to capacitive loading effect. Such external test-input access pin would capacitively load the circuit at the opto-electronic interface, and would severely limit the transmission bandwidth for both the normal communication mode and for the test mode.
Conventional testing, consisting of exposing the photodiode to light, requires accurate control of the optical-signal light intensity and of the ambient light intensity, during the entire testing procedure. The testing is not desired to be performed in the integrated circuit processing environment (wafer testing for instance) because of inconvenience and high cost. It is desirable to have a testing device to test the transimpedance amplifier using only electric signals and components (and neither using optical signals nor using optical components).
U.S. Pat. No. 5,585,731, issued to Tsuchida et al. (hereinafter xe2x80x9cTsuchidaxe2x80x9d)is directed to a test circuit for testing a transimpedance amplifier. The test circuit accepts an input voltage and then causes a test current to be drawn from the transimpedance amplifier. FIG. 2 shows a design of the Tsuchida""s test circuit 200. The Tsuchida""s test circuit 200 comprises a current mirror circuit 210 having two NPN (or PNP) transistors for generating a test current. However, the capacitive loading by the Tsuchida""s test circuit greatly reduces the frequency response of the overall circuitry. Therefore, a new design of a test circuit for the transimpedance amplifier is needed.
It is therefore an object of the present invention to provide a novel method and apparatus to test a transimpedance amplifier.
It is a further object of the present invention to perform in-circuit testing of the integrated optical transimpedance amplifier without the need to expose the photodiode to different light intensities, and without the need to disconnect the photodiode from the transimpedance amplifier.
It is another object of the present invention to provide a testing circuit for testing the transimpedance amplifier without creating a high capacitance loading to the amplifier.
It is a further object of the present invention to integrate the testing circuit with the signal (path) circuit.
It is the object of this invention to have the test circuit configured symmetrically balanced, such that there is no DC current component flowing to/from the transimpedance amplifier input and causing DC offset voltage at the transimpedance amplifier output in the absence of any signals.
It is therefore another object of the present invention to provide a testing circuit that is simple in design and is able to be built on the same common semiconductor substrate as that of the photodiode and as that of the transimpedance amplifier.
The present invention discloses a two-stage transimpedance circuit in which the first stage (i.e. a current mirror) performs dual function. This innovative dual function first stage design comprises a balanced, symmetrical, current mirror stage. According to the present invention, the first stage of the amplifier can either work as a high-frequency current mirror for mirroring current signals from the photodiode to the transimpedance amplifier, or being used as a BIST circuit for testing the transimpedance amplifier connected to the photodiode, in which case the mirror accepts voltage inputs from an outside test pin and the photodiode is not exposed to light. No switching is required to activate/deactivate the test mode (it is always on).
Specifically, this dual-function current mirror stage (hereinafter xe2x80x9cDFCM stagexe2x80x9d)of the present invention comprises an output driver having two complementary transistors connected in series. Each of these two complementary transistors is part of one current mirror of two pairs of current mirrors internal to this circuit. According to the present invention, the two current mirrors are connected in series such that a same DC bias current flows through both two complementary transistors of the output driver. Thus, the DC output offset current of the DFCM circuit is minimal, and is only depending on the device geometries of the two output transistors. Typically, the DFCM output offset currents are 1/1000 to 1/10000 of the DFCM bias current.
Furthermore, according to another aspect of the present invention, each of the transistors in the two current mirrors pair inside the DFCM is buffered by a series transistor to form a cascode design. Two advantages are obtained by utilizing this cascode topology.
First, the cascode configuration reduces by a factor of 1000 to 10000 the DC current mismatch associated with the current mirrors inside the DFCM and present, if any, at the output of the DFCM. Specifically, the cascode devices cancel the Early effects (mismatches) inside the internal current mirrors of the DFCM by equalizing the VDS bias points of the mirror devices.
In addition, the cascode configurations also improves the overall AC frequency bandwidth of the DFCM. The cascode devices eliminate the Miller capacitance effects on the transistors in the output stage of the DFCM. Therefore, the BIST circuit achieves very high frequency response (e.g. 4 GHz for a typical 0.6 xcexcm CMOS process).